High speed of memory access, and reduced power consumption are features that are demanded from semiconductor devices. In recent years, there has been an effort to reduce power consumption and increase access speed for semiconductor devices. As part of that effort to reduce power consumption, it may be desirable to use a level shifter circuit. The level shifter circuit provides a peripheral voltage (VPERI) for operating peripheral circuits throughout the semiconductor device. The peripheral voltage (VPERI) is typically lower than a power supply voltage provided to a semiconductor device (VDD).
FIG. 1 is a circuit diagram of an example level shifter circuit in a semiconductor device. The level shifter circuit 10 includes inverters 11 and 12 arranged in series. The level shifter circuit 10 may convert a signal with a high voltage (e.g., the power supply voltage (VDD)) into a signal with a low voltage (e.g., the peripheral voltage (VPERI)). Signal characteristics of waveforms of the signal may change due to conversion of the signal from the signal with the high voltage into the signal with the low voltage. Several factors may cause the changes in the signal characteristics. For example, the several factors may include transition times (TT) of the signals and threshold levels (TL) of input and output signals of the level shifter circuit 10.
FIG. 2 is a timing diagram of signals in the level shifter circuit of FIG. 1. A signal makes transitions, such as a rise from a logic low level to a logic high level during a rise time (tR) and a fall from the logic high level to the logic low level during a fall time (tF). The signal has transition edges, such as rising edges and falling edges. An input signal (1) of the inverter 11 has a voltage having an amplitude (VDD) shown as a level VDD and the input signal rises from the logic low level to the logic high level represented by the voltage VDD during a rise time (tR) (3) and falls from the logic high level to the logic low level during a fall time (tF) (4) in FIG. 2. An output signal (2) of the inverter 12 has a voltage having an amplitude (VPERI) shown as a level VPERI and the output signal rises from a logic low level to a logic high level represented by the voltage VPERI during a rise time (tR) (5) and falls during a fall time (tF) (6) in FIG. 2. For example, the power supply voltage VDD may be 1.5V and the peripheral voltage VPERI may be 0.8V.
A threshold level (TL) represents a voltage above which a signal is considered to be a logic high level and a signal below the threshold level (TL) is considered a logic low level. In general, a waveform of the signal may be divided into two sections, a high-pulse section where the signal is above the threshold level (TL) and a low-pulse section where the signal is below the threshold level (TL). The threshold level (TL) may be approximately 50% of a signal. A signal having an amplitude VDD may be divided by the TL of VDD, which is ½ VDD. A signal having an amplitude VPERI may be divided by the TL of VPERI, which is ½ VPERI. Thus, the level shifter circuit 10 has different threshold levels ½ VDD and ½ VPERI for the input signal and the output signal, respectively. For example, the signal having the amplitude VDD and the signal having the amplitude VPERI having similar rates of voltage rise and voltage fall may have different rise times and fall times due to different amplitudes. In this example, durations of a logic low level before and after the level shifter circuit 10 become very different, even if durations of a logic high level between the rise time and the fall time remain constant before and after the level shifter circuit 10. Thus, a duty cycle of the output signal of the level shifter circuit 10 may be different from a duty cycle of the input signal of the level shifter circuit 10 when a cycle period is the same while rise times and fall times are different as shown in FIG. 2.
TABLE 1Cycle periods, duty cycles, rise and fall times of a level shifter circuit.CycleDutyperiodcycleFall timeSignal(ps)(%)Rise time (tR) (ps)(tF) (ps)Amplitude: VDD100050.0400 ((3) in FIG. 2)400 ((4)in FIG. 2)Amplitude: VPERI100031.7213 ((5) in FIG. 2)213 ((5)in FIG. 2)
Table 1 shows an example of cycle periods, duty cycles, rise and fall times of signals of the level shifter circuit 10 as shown in FIG. 2. In this example, the duty cycle of the output signal is 31.7%, which is lower than the duty cycle of the input signal, 50%. Thus the duty cycle of the signal is distorted from 50% to 31.7%.
Recently, duty cycle correction using adjustments in sizes of p-channel and n-channel transistors and a number of fan-outs of the transistors in level shifter circuits have been implemented, in order to maintain signal characteristics before and after level shifting without distorting a duty cycle. For example, different numbers of fan-outs are assigned to a rise transition and a fall transition, so that durations of the high-pulse section and the low-pulse section are adjusted to maintain the duty cycle. However, duty cycle adjustments in sizes of transistors or a number of fan-outs, pose several problems.
First, the duty cycle correction may cause unexpected results if transistor characteristics are unbalanced between the p-channel and n-channel transistors in the level shifter circuit. Duty cycle distortion due to variation of transistor characteristics among chips may not be adjusted by the above size and fan-out adjustments.
Second, the sizes of the transistors are determined in a product design phase, assuming that voltage levels of the input/output signals remain constant. For example, U.S. Pat. No. 7,835,213 discloses a level shifter circuit used in dynamic random-access memory (DRAM) including a memory cell array, input/output buffers and peripheral circuits between the memory cell array and the input/output buffers having transistors fine-tuned threshold voltage and thickness of gate insulation film. However, this type of level shifter circuits may not be able to handle changes in the input signal, such as a source voltage. The DRAM including such a level shifter circuit, therefore, is not suitable for applications where the DRAM may receive a source voltage different from the source voltage assumed in the product design phase.